Design and validation of a multilevel voltage source inverter based on modular H-bridge cells

Graphical abstract


Multilevel Power Converter Integration
shows the final scheme implemented in the design of the multilevel converter. The system consists of a MicroLabBox dSPACE controller device for implementing different control algorithms. This development device makes it possible to perform experimental tests and/or measurements quickly and easily, mainly due to its programming environment based on MatLab/Simulink software and its native application for developing SCADA-type graphical interfaces. DSP's high computational power and low I/O latencies provide good real-time performance [5].
The MicroLabBox dSPACE interacts with the physical system of the experimental test bench through measurement and signal conditioning circuits, obtaining the necessary variables for the control algorithm, which are the load currents and the converter's output voltage. Once the external information is obtained, the control algorithm calculates the switching vectors for each H-bridge cell, sending trigger signals through the GPIO outputs of the controller, which operate at TTL levels (5 V). Finally, the trigger signals are transmitted through an optic fibre link to the SiC-MOSFET trigger control board, integrated into the power board with signal conditioning circuits and noise levels reduction generated by the semiconductor switching.

H-bridge cell design based on SiC-MOSFET
The block diagram of the proposed H-bridge cell with the power board is shown in Fig. 2. The control signals are received via an optic fibre link to reduce electrical noise levels in the digital control circuits and measurement systems, using the HFBR-2521Z optic fibre receiver [6]. Subsequently, the received PWM signals are sent to the block, generating the necessary complementary trigger signals for each branch of the H-bridge. This logic circuit implements the dead time between a PWM signal and its complement. It is achieved using 74HC86 XOR gates and resistive and capacitive elements to generate the dead time delays. The driver for the SiC-MOSFETs is implemented using the IR2110S integrated circuit. The SiC-MOSFET CAS120M12BM2 is used to assemble the design power stage. Their independent power supply is implemented by DC/DC converter CC10-1212SF with galvanic isolation to achieve modularity of each H-bridge cell.

Trigger control circuit for H-bridge
PWM signal conditioning: The PWM signals transmitted from the dSPACE control device must be conditioned to eliminate or attenuate the presence of oscillations or overshoot during transitions between voltage levels at high frequencies. Signal conditioning is imple-  mented using the ISO7240 integrated circuit, which provides galvanic isolation up to 2500 V RMS for 1 min [7]. These devices allow high voltage blocking, isolate grounds, and prevent noise currents from entering the local ground, interfering with or damaging sensitive circuits. Fig. 3 shows the design based on ISO7240, according to design guidelines provided by the manufacturer [8].
The RC filter used at the output of each channel of the ISO7240 is used to reduce the overshoot during transitions between logic levels. It is considered that the maximum switching frequency will be 100 kHz. Therefore, it is chosen to size the filter with a cut-off frequency higher than the maximum operating frequency in such a way that it generates significant phase shifts. The values used for the low pass filter are R = 100 X and C = 100 pF, obtaining an approximate cut-off frequency of 1.59 MHz.
Complementary PWM Signal Generation and Dead Time: In real applications, any signal transition can be considered as a very fast falling or rising ramp [9] instead of perfect transitions, which would cause damage to the power devices due to current overshoot caused by small short circuits during the rising or falling transitions of PWM signals. The circuit in charge of generating the complementary signals and dead times is shown in Fig. 4. The implementation contemplates a similar scheme for each required PWM channel.
Dead time is determined according to the characteristics of trigger driver ICs for SiC-MOSFETs. This is mainly due to the delays generated by on (t on ) and off (t off ) times. The manufacturer's technical data sheet of the gate driver device manufacturer for the SiC-MOSFET indicates these times t on = 120 ns and t off = 120 ns. The SiC-MOSFET used is the CAS1201012BM2, it has these times t on = 38 ns and t off = 70 ns, therefore a dead time t d = 1 ls has been implemented. The assigned value to the dead time is set by elements R2-C2 and R3-C16 as seen in Fig. 4, diodes D5 and D6 should be of the fast switching type. PWM signals, together with their complement, pass through an Low pass filter (LPF) formed by R5-C5 and R4-C4 to reduce the existing over-peaks or ripples at the output of the stage without adding a significant phase shift to these signals.
Trigger control for SiC-MOSFET: A design based on commercial integrated circuits for H-bridge control is developed for the switching control of the power semiconductors of the H-bridge cells. The IR2110S integrated circuit of the International Rectifier company has been used to implement this design [10]. The IR2110S is a high-speed MOSFET and IGBT driver with independent high and low trigger where Q g is the total gate terminal load, Q ls the required load level change per cycle, V LS is the voltage drop across the bottom SiC-MOSFET, V f the voltage drop across the direct biased Bootstrap diode and I qbsðmaxÞ is the maximum quiescent current value for the high side of the driver (upper SiC-MOSFET). The values used are shown in Table 1.
For the calculations, the term I cbsðleakÞ f and V min are disregarded because the capacitors are not electrolytic. The final value resulting from the calculations for the C bs capacitor is 74.6 nF, for which 100 nF has been used as the final value. PCB board designed for the trigger control circuit: Fig. 6 shows the final PCB resulting from the detailed design in previous sections. The image shows the most representative parts of the PCB.

Design of the power circuit for the H-bridge
The proposed solution for designing the multilevel converter is the integration of cells in an H-bridge configuration connected in series to obtain higher output voltage levels. This latter allows for meeting the objective of a scalable and modular design. Table 2 shows the most relevant design criteria that are taken into account for the power stage.
To achieve this objective, the DC-link must be implemented through a floating voltage, i.e., not referenced to GND, and simultaneously independent in each H-bridge cell. The power stage allows optional implementation of DC-link by using external DC power supplies for each DC-link voltage.
DC-link voltage calculation: The maximum DC-link voltage for each H-bridge cell must be such that it can be implemented in various multilevel configurations, operating with a significant safety margin. For this converter design, calculations were performed considering a maximum DC-link voltage for each cell of 400 V.  In addition, if the DC-link voltage is 400 V, it is possible to obtain an output voltage per phase of 1200 V with three Hbridge cells, thus, it is possible to operate with a large safety margin in 220/380 V grids. The value of the capacitor for the DC-link can be expressed by (2).
being the power value P nom = 1000 W, the voltage over the capacitor V DC = 400 V, with a variation of 1% in DV DC = 4 V, resulting in a minimum value of C = 497 lF.

Power semiconductor devices:
The SiC-MOSFET CAS120M12BM2 from CREE Semiconductor is a two-transistor power module with a breakdown voltage of 1200 V for a current value of 138 A for a 90 C temperature and a low conduction resistance with a high switching speed, higher than traditional switching devices such as IGBTs. Table 3 shows the most relevant parameters of the selected SiC-MOSFET [11]. Then, to avoid damage to the H-bridge cell due to voltage transients that may occur, a safety margin in voltage and current levels of 80% is proposed for the selection of the switching devices. Therefore, the levels to be withstood by the SiC-MOSFETs are 720 V and 15 A, respectively. Further-   more, it is observed that the selected device, the CAS120M12BM2 meets the maximum voltage, maximum current, power dissipation and speed requirements demanded by the proposed design for the multilevel converter. Snubber network design for the switches: Electronic switches are the fundamental element of all power converters. To obtain high performance of the converter switching device, it is necessary to design damping networks, also known as snubber networks, to reduce phenomena such as voltage surges and transient damping caused by circuit inductances when switching a transistor. These phenomena can exceed the devices' physical limits, resulting in the degradation or destruction of such devices. These transients can be detrimental to electronic devices and can adversely affect system efficiency and reliability. A snubber network provides an alternative path for the current and absorbs the energy stored during switching [12].
The selected snubber network for the power board design is the RCD-type network. This circuit topology finds a wide field of application in the protection of power switches, such as bipolar transistors or IGBTs, due to its simplicity and efficiency [13]. The schematic representation of the selected snubber network is shown in Fig. 7.
The value of the required capacitance for the snubber network is determined by the following Eq. (3), which determines the minimum value required for the design conditions.
where L M is the parasite inductance value, V DSP2 corresponds to the DC peak voltage over the capacitor C s ; I off is the off current and V DD is the DC-link voltage value. The following values were used: L M = 15 nH, V DSP2 = 480 V, V DD = 400 V y I off = 8 A to determine the capacitor value C s , resulting in an approximate value of C s = 150 pF. To calculate the resistance value R s we used Eq. (4).
Considering the maximum switching frequency of f s = 100 kHz, and assuming the value of C s previously obtained by 3, the approximate value of R s = 28.9 kX is obtained. The connected diode to the following elements, R s y C s , has to be of fast switching type and capable of operating in the current ranges of the H-bridge scheme. The selected component is the ST2045A diode, a Schottky diode capable of driving an average current of up to 20 A and a maximum peak current of 250 A. A network made up of a diode, and a resistor is added to the snubber input at the gate terminal of the SiC-MOSFET, as shown in Fig. 7.
This arrangement generates a small activation delay without affecting the SiC-MOSFET turn-off, providing additional dead time. The resistor-diode network is used to reduce the overshoot that exists during the reverse recovery time of the device. On the other hand, the IR2110S controller can deliver a current of up to 2 A at its outputs during the trip. This allows limiting the value of said current delivered at the gate terminal of the SiC-MOSFET. For this, a resistor is used R g = 47 X, being the trigger voltage at the output of the gate terminal V gs = 12 V, resulting in an output current of I o = 250 mA for that voltage.
An RC low-pass filter is implemented in the input circuit, which reduces the overshoots and oscillations of the signals coming from the IR2110 controller. The RC filter capacitor results from the parasitic capacitance of the SiC-MOSFET, which has a value of C iss =6,3 nF according to the manufacturer's manual, while the external capacitor used for the filter has a value of 7.8 nF. The resistor connected to the gate terminal of the device has a value of R g = 47 X, resulting in a cutoff frequency equal to f 0 = 434 kHz.
PCB board resulting from the design of the power circuit: has connectors to connect to the trigger controller board for the SiC-MOSFETs, as well as mounting points to provide mechanical rigidity to the trigger controller board/power board assembly.
Final assembly of the H-bridge cell: Fig. 9 shows the final assembly of the H-bridge cell, made up of the power board and the trigger controller board. These boards are interconnected through two 5x2 header-type connectors, one of the connectors for signal transfer and the second for supply voltages.

Voltage Signal Conditioning
To implement the control algorithms, it is necessary to carry out the measurement and conditioning process of the signals corresponding to the relevant electrical variables for the various algorithms. The scheme of the acquisition voltage signals is shown in Fig. 10.   In the voltage measurement circuit, an initial stage consisting of a resistive voltage divider is used to connect the electrical network signal to be processed. The resistive divider is necessary to reduce the voltage amplitude to manageable levels by the INA826 low noise instrumentation amplifier used for the proposed design [14]. The scheme for the input stage of the voltage sensor is observed in Fig. 11.
The input voltage divider is designed for a maximum input voltage of 380 Vrms, equivalent to 537.39 Vp. The maximum input level is set to 600 Vp. The input voltage divider provides 0.003323 attenuations to the measured voltage, resulting in a voltage of 1.9938 Vp at the input of the INA826. The gain of the INA826 instrumentation amplifier is given by (5): The selected RG value is RG ¼ 5:6 kX, with which a profit of 9.82 units is obtained. Subsequently, the obtained signal at the output of the INA826 is taken to the second amplifier stage, made up of an ultralow noise operational amplifier of the OPA27/OPA350 series [15,16], which is also responsible for modifying the DC offset level and providing a second amplification of the conditioned signal. Fig. 12 shows the schematic of the measurement and conditioning circuit for voltage signals.  The printed circuit design allows the voltage meter to be adapted to output levels of AE 10 V and 0-3 V, respectively. This is possible by modifying the second amplifier stage, selecting the OPA27 for the AE 10 V case or the OPA350 for the 0-3 V case. In addition, when selecting the operational amplifier for this stage, the supply voltages must be modified according to the case. This is achieved by modifying R5-R6 for the positive supply and R7-R8 for the negative supply. This stage is configured to obtain unity gain, being able to modify the offset level by using preset R4. In addition, the necessary capacitive filters are implemented to provide a good response to power interference. The voltage sensor board implements a galvanically isolated power supply using an IH0512S galvanic isolation switched DC/DC supply [17]. Fig. 13 shows the schematic circuit of the isolated source.
Using IH0512S, the voltages AE 12 V are set, from which the other necessary voltages are obtained in the case of requiring the use of the OPA350 for a 0-3 V output. This is achieved through the use of 3 V voltage regulators.
PCB board resulting from the voltage sensor design: The implementation of the voltage measurement and conditioning circuits on modular printed circuit boards can be seen in Fig. 14.

Current signal conditioning
The circuit diagram for the measurement and conditioning of current signals is shown in Fig. 15. The first stage implements the ACS780xLR sensor [18], a current sensor integrated circuit designed to measure AC and DC currents up to 100 A. The ACS780xLR sensor, for a maximum input range of AE50 A, has a sensitivity of 40 mV/A according to   its datasheet, resulting in a maximum output value of 2 V. Subsequently, the output signal obtained from the ACS780xLR sensor is sent to the amplifier and offset level adjustment stage, which stage is configured with unity gain. The design of the printed circuit allows adapting the output voltage level to output levels of AE 10 V and 0-3 V, respectively. This is possible by modifying the second amplifier stage, selecting the OPA27 for the AE 10 V case or the OPA350 for the 0-3 V case, just like the voltage sensor circuit. To select the OPA27, use R8 and R9, while the OPA350 uses R7. The integrated circuits have capacitive filters to reduce the levels of electrical noise in their feeds. Fig. 16 shows the schematic of the circuit corresponding to the current input level reduction stage. The current sensor board uses a galvanically isolated power supply through the IH0512S switched DC/DC power supply, from which the voltages AE 12 V are obtained, and the other voltages are also obtained, in case of the use of the OPA350 for a 0-3 V output. This is achieved through the use of 3 V voltage regulators. Fig. 17 shows the schematic of the circuit that implements the board's power supply.
PCB board resulting from current sensor design: The implementation of the current measurement and conditioning circuits on modular printed circuit boards can be seen in Fig. 18.    Fig. 19 shows the final assembly of the 7-level CHB converter, in which the main elements are observed: the H-bridge cells (power board and controller), voltage and current sensors, the controller device and finally, the PC where the measurements are displayed in real-time. Each of the boards mentioned has a modular and scalable design, in such a way as to facilitate changes in the converter configuration according to the end user's requirements. In addition, this modular structure facilitates the replacement of damaged parts.

Build instructions
Regarding the designs of printed circuits, it can be mentioned that all the integrated circuits (IC) used to assemble them are SOIC-type surface mounts. For cases in which there are no integrated libraries of their own, they were designed to make up for that lack. The schematic diagram and PCB layout were developed using the Altium Designer application. The designed boards are routed to two layers to reduce the dimension of the resulting board, different ground planes were used on both sides for digital and analogue grounds, in addition to implementing galvanic isolation towards the controller side, thus reducing interference. generated during the switching process of the H-bridge cells. The trigger PWM signals are sent through an individual optic fibre link, from the controller GPIO modules to an optic fibre transmitter board, these signals are then processed on the controller boards of each H-bridge.
Before the tests and calibration process of each board, all the tracks of each of the boards were subjected to quality tests, verifying the continuity and insulation of each section. For the assembly process of each board, a standard procedure was followed, where the first to be assembled was the surface solder elements, followed by the through-encapsulation components and finally the connectors. Component names are clearly labelled on the PCB silkscreen and correspond to the names on the material lists.
Finally, for the assembly of the power converter hardware, a reinforced metal structure with a capacity for six levels is selected, where each level is a metal tray that is used as a base to house instrumentation equipment, sensors and the Hbridge cells, with cascade arranged.   On the other hand, in the photograph of Fig. 21 (a), shows the three-phase sockets corresponding to the connection of the multilevel converter, which consists of a 4-pole three-phase connector with a capacity of 16 A together with its 16 A thermomagnetic protection key (Circuit Breaker 1). Likewise, the connectors correspond to the output of the multilevel converter, which has its own protection consisting of a 16 A three-phase thermomagnetic key (Circuit Breaker 2). Fig. 21 (b) shows the three-phase test load used for the experimental tests, Fig. 21 (c) presents the output filter for the converter, and finally Fig. 21 (b) shows one of the DC sources used for the DC-link.

Operation instructions
The recommended procedure for operating the converter is as follows: Connect the load for use in the three-phase output socket (VSI output). Connect the mains power to the corresponding three-phase socket (Electrical grid) Activate Circuit Breaker 1 to power the converter Turn on the controller (MicrolabBox) and the data monitoring PC. Activate Circuit Breaker 2 for protection at the output of the power converter. Activate the output contactor to supply the three-phase load.
Among the precautions to be taken into account during the start-up process, we have the verification of the correct connection to the electrical network so that the circuits and control and measurement are all in an operational state, for this, each designed board has an indicator light for quick visual inspection.

Analysis of the H-bridge cell
The test platform for the H-bridge converter is shown in Fig. 22. The scheme consists of two independent modules, which are the controller board or driver for the SiC-MOSFETs and the power board. In addition, a MicroLabBox-dSPACE controller is used for the implementation of the control algorithms and generation of PWM trigger signals. The output signals are measured on the load and captured through the use of digital oscilloscopes. In this context, the specifications of the experiment, designed to verify compliance with the proposed design objectives, are shown in Table 4. Fig. 23 shows the experimental test platform to obtain the preliminary results of the H-bridge cell, used to characterise the design proposal to be implemented in the multilevel VSI.     The trigger signals corresponding to each SIC-MOSFET that make up the VSI are represented in Fig. 24 (a). Those trigger signals are obtained at the outputs of the complementary signal generation circuits and dead time present on the firing control board. According to the results, the generated signals present good electrical characteristics considering the low level of noise observed and the delays due to the settling times of the signals. The Fig. 24 (b) shows the result of the generation of dead time by hardware. It has a value of 1 ls for a frequency of 20 kHz.
It is important to mention that the dead time value can be adjusted according to the switching frequency to be used. This time is essential to avoid the momentary short-circuit existing between the activation and deactivation of the switches of the same leg of the VSI, and this in turn would generate power losses and a decrease in the performance of the system. The power board consists of the signal conditioning circuits for each SIC-MOSFET, consisting of passive filters for damping overshoots that could occur in the signals coming from the controller integrated circuits for SIC-MOSFETs. In order to facilitate the analysis of the scheme, relevant measurement points are added. The DC link to be used for the design has a maximum value of 480 V. Fig. 25(a) shows the PCB layout for the power board.
The output signals for the H-bridge cell are shown in Fig. 25(b). These output signals are essential to guarantee proper operation of the switching system and ensure effective current and voltage control at the load. The obtained results adequately comply with the proposed design, according to captured signals by the oscilloscope. Fig. 26 (a) shows the test platform used in the laboratory for the experimental validation of the voltage sensor. It allows measuring AC voltages up to 380 Vrms. Fig. 26 (b) presents the captured waveform, by the oscilloscope, of the voltage signals. Fig. 27(a) shows the test platform used in the laboratory for the experimental validation of the current sensor. Fig. 27(b) presents the evolution of the measured current when using a resistive load.

Current Sensor Validation
Finally, Fig. 28 shows the superposition of both measurements, observing a negligible phase shift between the voltage and current measurements on the load, which is a desirable characteristic at the moment of the implementation of control algorithms.

Experimental results of the multilevel VSI
The experimental platform of the multilevel VSI is made up of H-bridge cells interconnected in cascade, where each Hbridge cell consists of an independent DC-link that is applied through continuous sources and provides the necessary energy to the switching devices for the generation of output voltages that are injected into the load at the common connection point (PCC). In this mode of operation, series-connected SiC-MOSFET switching devices and an R-L inductive filter are integrated into the VSI's output. This filter reduces the effect of the harmonic components resulting from the switching of the power devices that make up the VSI. Fig. 29 denotes the configuration of the experimental platform for use in multilevel VSI mode.
For this paper, a preliminary analysis was conducted using simulation tools for the multilevel converter with 5-level and 7-level voltage schemes prior to experimental measurements. The obtained results from the simulation are shown in Fig. 30. Fig. 30(a) and Fig. 30(b) display the output voltage and current waveforms of the converter for the cases of 5 levels and 7 levels, respectively. Fig. 30(c) and Fig. 30(d) show the levels of total harmonic distortion (THD).
For the 5-level converter, a THD of 3:78% is obtained, while the 7-level converter exhibits a THD of 2:51%. It can be observed that the 7-level converter has a lower harmonic content, as indicated by previous studies.
To verify the proper functioning of the designed power converter, experimental results are obtained from the multilevel VSI test platform, in which a predictive current control is implemented. To achieve the proposed objective, it is initially considered that the VSI regulates the current injected into a pure resistive three-phase load, also assuming the following parameters; DC-link voltage, Vdc = 30 V, switching frequency f s = 33 kHz and load R L = 16X.
The output signal of the power converter v / c , as well as the generated current for the phase i / c from the references and as a result of implementing a classic predictive control without modulation, is seen in the oscilloscope screenshot, shown in Fig. 31(a). On the other hand, the obtained three-phase currents by the converter in multilevel VSI mode are observed in Fig. 31(b). It can be seen in these graphs that the applied currents to the three-phase load are generated in the correct sequence, yielding a low harmonic distortion content, which is to be expected thanks to the ability of the multilevel converter to generate sinusoidal signals.
One of the most important sources of harmonic generation in electrical installations is power converters. To properly understand the adverse effects on the electrical system, it is important to determine the level of harmonics introduced by the proposed VSI design [19]. For this, a study of the total harmonic distortion (THD) level introduced by the converter is     carried out through the obtained measurements from the current and voltage signals. This THD level result was obtained using the fast Fourier transform, an oscilloscope function. Mathematically speaking, THD is defined as: where i s1 is the fundamental component of the measured currents and i sj are the harmonic currents.
For the experimental validation of the design, the analysis of Total Harmonic Distortion (THD) of the system has been conducted for the case of the 7-level converter. The THD has been measured in each phase of the multilevel converter. Fig. 32 shows the results from the calculations of the level of THD of the output current of the multilevel VSI, applied to the load. Fig. 32 presents similar levels of THD results for each phase, with values of 4:60% for phase a, 4:50% for phase b, and 4:26% for phase c.
Subsequently, a study of the dynamic behaviour of the multilevel converter is carried out, adjusting parameters representative of the desired output signal, such as the frequency and amplitude of the output current. Fig. 33 shows the obtained results in the output signals of the multilevel VSI with reference changes in the amplitude in the implemented control algorithms.  It is observed that the converter presents a good dynamic response to the change of reference amplitude, managing to modify such amplitude in a considerably short time. The calculated mean square error (MSE) between the reference signal and the measured value is 0.081 A.
On the other hand, Fig. 34 shows the obtained results in the output signals of the multilevel VSI before changes in the frequency of the generated reference. A good dynamic response of the converter to rapid changes in the reference frequency is also observed. Also, for the dynamic analysis of the reference frequency change, the MSE analysis between the reference and the measurement was performed, resulting in a value of 0.08 A.
Finally, the efficiency of the designed H-bridge cells was calculated by determining the power losses due to conduction and switching for an individual H-bridge cell based on SiC-MOSFET devices. The following equations are used to determine conduction losses (7) and switching losses (8).
being I Drms the drain current root-mean squared (rms), f s the operating frequency, V DD the DC-link voltage, R DSðonÞ the drain source resistance, t on and t off the state transition time intervals, turn-on and turn-off, respectively. Laboratory tests were performed for an individual H-bridge cell, two power values, 0.5 kW and 1 kW, were considered for the test. In turn, the switching frequency range of 50 kHz to 200 kHz was analyzed. As observed in Fig. 35, the power losses increase with frequency, and with it the efficiency decreases, maintaining an efficiency higher than 95% in all cases.

Conclusion
This article has addressed in detail the design and then the experimental validation of different electronic circuits that make up the multilevel power electronic converter based on H-bridge cells with a modular structure. For the design of each circuit, the recommendations are present in the design guidelines, aligned with the datasheets of the manufacturers of the different electronics employed.
Regarding the experimental results, tests were carried out for all the proposed designs to corroborate the correct functioning of the circuits and ensure that they meet the design objectives. Calibration tests of the voltage and current sensors were carried out, as well as the experimental verification of the correct operation of the firing control circuits of the SiC-MOSFETs of each H-bridge cell.
A seven-level voltage source inverter has been designed to synthesise a three-phase alternating current output of the indicated value by its reference with a relatively low THD percentage of 4.45% on average, resulting in a value lower than the maximum recommended by the quality standards. In addition, tests were carried out to determine the correct dynamic operation of the converter through changes in the amplitude of the reference, as well as in the desired output frequency. These analyses gave a satisfactory result. As for the energy efficiency of the designed H-bridge cell, the efficiency is greater than 95% according to the experimental tests carried out for operating frequencies between 50 kHz and 200 kHz, noting that the efficiency decreases as the operating frequency increases due to losses caused by switching.

Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.